The present invention relates to a PLL circuit, a semiconductor device, an electronic control unit, and a control method of a PLL circuit. For example, the present invention relates to a PLL circuit, a semiconductor device, an electronic control unit, and a control method of a PLL circuit which are suitable for adjusting the phase of an output clock signal with a high accuracy.
An automobile is equipped with an angular velocity sensor that detects an angular velocity; an acceleration sensor that detects an acceleration; and an electronic control unit (ECU (Electronic Control Unit)) that performs brake control and engine control to prevent a side slip of the automobile, and controls the operation of an airbag, based on detection results from the angular velocity sensor and the acceleration sensor.
The electronic control unit is provided with a PLL circuit that generates an output clock signal by using a resonance signal from the angular velocity sensor as a reference clock signal. A clock signal orthogonal to the reference clock signal is generated based on the output clock signal. The electronic control unit multiplies a modulated signal (a signal obtained by modulating the resonance signal with a sensitivity signal), which is output from the angular velocity sensor, by the clock signal orthogonal to the reference clock signal, thereby detecting only sensitivity signal components (angular velocity components) from a modulated signal.
In order to accurately detect the sensitivity signal components, the PLL circuit is required to reduce the deviation of the phase of the output clock signal from the phase of the reference clock signal as much as possible. In other words, the PLL circuit is required to accurately adjust the phase of the output clock signal.
Japanese Unexamined Patent Application Publication No. 2013-77966 discloses a technique relating to a PLL circuit. The PLL circuit disclosed in Japanese Unexamined Patent Application Publication No. 2013-77966 includes a pulse signal generation unit, a charge pump, a low-pass filter, and a voltage control oscillation circuit. The pulse signal generation unit generates a pulse signal according to a multi-level reference signal having a periodicity. The charge pump switches ON/OFF of the output current according to the pulse signal. The low-pass filter generates a control voltage according to the output current. The voltage control oscillation circuit generates an output clock signal having a frequency according to the control voltage. The PLL circuit adjusts the amount of current when the output current is turned on according to the reference signal. Thus, the PLL circuit improves the accuracy of the phase adjustment of the output clock signal.